In general terms, a process for fabricating a semiconductor device involves transferring an integrated circuit (IC) layout to a semiconductor chip, which typically includes: first forming the IC layout on a mask to form a mask pattern thereon; and then transferring the mask pattern onto the semiconductor chip.
However, due to continuing shrinkage of critical dimensions of the semiconductor devices as well as resolution limits of exposure tools, a phenomenon referred as optical proximity effect (OPE) is prone to occur when to expose and transfer mask patterns arranged with a high density. This OPE effect can lead to defects when transferring the mask patterns onto the chip, common examples of which include right-angled corner rounding, line end shortening and line-width variations (including both increases and decreases).
For this reason, in the existing photolithographic process, optical proximity correction (OPC) is typically performed on mask patterns prior to mask fabrication to compensate for the optical proximity effect caused by a limited resolution of an optical system employed in the exposure tool. For example, FIG. 1 shows a flow chart illustrating a typical OPC method for mask pattern compensation employed in conventional IC fabrication processes. As illustrated, the OPC method includes: providing data of original design patterns; establishing a single OPC model; modifying the original design patterns with the OPC model; and obtaining data of post OPC patterns.
On the other hand, with sizes of patterns to be exposed continuously decreasing and being reduced to the 65-nm technology node, layout patterns are of higher complexity and hence require an improved OPC compensation accuracy which typically leads to exponential increases in OPC processing time as compared to those at technology nodes of 65 nm and above. The elongation of OPC processing time increases difficulties in controlling and reducing the tape-out cycle time and in optimizing the utilization of OPC hardware and software resources. As can be seen in FIG. 2, with the technology node shrinking from 130 nm to 22 nm, the processing time of each level OPC calculation and simulation increases exponentially, and the smaller the technology node, the sharper the processing time increases and the more times the hardware and software resources are required.
Since such increases in OPC processing time can elongate the tape-out cycle time, there is an urgent need in the art for further optimization of OPC resource utilization and the reduction of OPC processing time.